The electronics industry continues to rely upon advances in semiconductor manufacturing technology to realize higher-functioning devices while improving reliability and cost. For many applications, the manufacture of such devices is complex, and maintaining cost-effective manufacturing processes while concurrently maintaining or improving product quality is difficult to accomplish. As the requirements for device performance and cost become more demanding, realizing a successful manufacturing process becomes more difficult.
A byproduct of the increased complexity of semiconductor devices includes uneven device surfaces, which become more prominent as additional levels are added to multilevel-interconnection schemes and circuit features are scaled to submicron dimensions. Typically, each level within the device is patterned, resulting in a surface with varied "step-heights" where metal forming the pattern remains on the surface.
Planarization is a term describing the surface geometry of a semiconductor device. Complete planarization occurs when the surface of the dielectric is flat, as in a plane. No planarization occurs when the surface of the dielectric directly models the "step-height" surface of the metal pattern in the layer underneath. The degree of planarization refers to the degree to which the varied surface geometry can be "planarized," or smoothed out into a planar surface. Varied surface geometry is often undesirable. Therefore, as additional layers are formed within devices, the required degree of planarization increases.
A commonly used new planarization process in semiconductor device manufacturing is chemical-mechanical polishing, or CMP. CMP is useful in the planarization of silicon wafers and of VLSI circuits between different manufacturing processes. CMP is a popular planarization method, due in part to its usefulness in the global planarization of semiconductor devices. Traditional planarization processes are restricted to effecting local planarity or topographical variation on a small scale, whereas CMP is often useful on a global scale greater than ten microns.
In one application, a CMP process involves securing a semiconductor wafer to a wafer holder with the wafer located face-down on a polish pad. Both the polish pad and the wafer holder rotate. A slurry, typically a colloidal silica that is a suspension of SiO.sub.2 particles, is applied to the process. The particle size typically varies from 100 angstroms to 3 microns. The slurry is generally applied using a wand feeding to the wafer holder and pad. The rate of removal of material from the wafer is a combination of chemical and mechanical rates. The mechanical removal rate is roughly proportional to the pressure and the relative velocity of the wafer. The chemical removal rate is a function of the size of the slurry particles and the solution pH, wherein the maximum removal rate is generally obtained using a slurry having a pH of about 11.5.
In addition to the use of slurry in the CMP process, a conditioner is also typically used for conditioning the polish pad. The conditioner aids in the CMP polishing process and contributes to the longevity of the pad. Another need in the CMP process is for adequately and efficiently cleaning the pad and the wafer itself. In clean room environments, it is important to maintain a CMP process that produces as few contaminants as possible. Since the slurry particle size ranges in the sub-3 micron range, clean-up is difficult and thus of high importance. In addition, it is helpful to prevent the byproduct resulting from the polishing of each wafer from accumulating on the pad and reaching additional wafers.
The traditional method for conditioning the pad and dispensing slurry is to use two separate mechanical components: a slurry dispense wand and a pad conditioner assembly. There are disadvantages in using two separate components. For instance, the slurry cannot be spread uniformly across the pad and may accumulate in the pad conditioning head. The non-uniform distribution of slurry distribution hinders the polishing process. In addition, the reaction byproduct cannot be thoroughly removed from the pad. When more than one wafer is processed at once, inadequate cleaning of the pad results in the reaction byproduct and other materials from one wafer coming into contact with other wafers. These disadvantages may result in, for example, long arc style scratches, shallow micro-scratches, inter-die thickness variation, and residual slurry particles. These disadvantages ultimately result in a significant yield lost and in reliability problems due in part to possible metal stringers in the shallow scratch area and surrounding residual slurry particles.